The invention pertains to a device structure and method for making JFET transistors at very small line widths which can overcome certain process problems caused by the small line widths.
As line widths have shrunk steadily down into the submicron range (today's line widths are 45 nanometers (NM) or 0.045 microns, where a micron is 10−6 meters and one nanometer equals 10 angstroms), all structures on CMOS, NMOS and PMOS circuits have shrunk including the thickness of the gate oxide. As line widths shrink, the voltages must be dropped to avoid punch through. This shrinking line width means the thickness of gate oxide must also be reduced so that sufficient electric field concentration to cause channel inversions in MOS devices can be achieved at the lower voltages. Shrinking gate oxide thickness causes leakage, which increases power consumption in CMOS circuits and all other MOS circuits. The limit of gate oxide thickness that will not cause leakage is about 50 nanometers, which has already been reached by the current state-of-the-art 45 nanometer line widths.
At one micron line widths, power consumption for a one square centimeter integrated circuit was 5 watts. As line widths shrink to 45 nanometers, power consumption for the same size chip could rise to 1000 watts. This can destroy an integrated circuit which is not cooled properly and is clearly unacceptable for portable devices such as laptops, cell phones etc. This power consumption complicates the design process immensely because it requires additional circuitry to put idle transistors to sleep so they do not leak. This power consumption is only one of the problems caused by shrinking line widths.
Prior art junction field effect transistors date back to the 1950's when they were first reported. Since then, they have been covered in numerous texts such as “Physics of Semiconductor Devices” by Simon Sze and “Physics and Technology of Semiconductor Devices” by Andy Grove. Junction field effect devices were reported in both elemental and compound semiconductors. Numerous circuits with junction field effect transistors have been reported, as follows:
1) Nanver and Goudena, “Design Considerations for Integrated High-Frequency P-Channel JFET's”, IEEE Transactions Electron Devices, Vol.; 35, No. 11, 1988, pp. 1924-1933.
2) Ozawa, “Electrical Properties of a Triode Like Silicon Vertical Channel JFET”, IEEE Transactions Electron Devices Vol. ED-27, No. 11, 1980, pp. 2115-2123.
3) H. Takanagi and G. Kano, “Complementary JFET Negative-Resistance Devices”, IEEE Journal of Solid State Circuits, Vol. SC-10, No. 6, December 1975, pp. 509-515.
4) A. Hamade and J. Albarran, “A JFET/Bipolar Eight-Channel Analog Multiplexer”, IEEE Journal of Solid State Circuits, Vol. SC-16, No. 6, December 1978.
5) K. Lehovec and R. Zuleeg, “Analysis of GaAs FET's for Integrated Logic”, IEEE Transaction on Electron Devices, Vol. ED-27, No. 6, June 1980.
In addition, a report published by R. Zuleeg titled “Complimentary GaAs Logic” dated 4 Aug. 1985 is cited herein as prior art.
A representative structure of a conventional N-channel JFET is shown in FIG. 1. The JFET is formed in an N-type substrate 10 and is contained in a P-well region 12. The body of the JFET is formed is shown at 14 which is an N-type diffused region containing source 16, channel 18 and drain 20 regions. The gate region 22 is P-type, formed by diffusion into the substrate. Contacts to the source, drain and gate regions are shown at 24, 26 and 28 and connections to these contacts are metal structures shown at 30, 32 and 34. The critical dimension of the JFET is the gate length shown at 38. It is determined by the minimum contact hole dimension marked at 36 plus the necessary overlap required to ensure that the gate region encloses the gate contact. The gate length 38 is significantly larger than the minimum hole dimension. This feature of construction of the prior art JFET limits the performance of these devices since channel length is substantially larger than the minimum feature size. In addition, the capacitances of the vertical sidewalls 40 and 42 of the gate diffusion to source and drain regions, respectively are also quite large. The gate-drain sidewall capacitance forms the Miller capacitance, a term known to those skilled in the art, and significantly limits the performance of the device at high frequencies.
Another problem with the JFET of FIG. 1 is that it is a normally on device. As such, it cannot be used to replace conventional CMOS transistors in today's integrated circuitry with the power leakage problems brought on by shrinking line widths. In order to substitute JFET's for CMOS to solve the power consumption problem at line widths of 45 NM and smaller, it is necessary to have a normally off JFET.
Therefore, a need has arisen for a process to fabricate normally off JFETs and a device structure, both of which eliminate the above noted etching problem and which will scale to smaller linewidths.